Field emission-type electron source and method of producing the same

ABSTRACT

A field emission-type electron source has a plurality of electron source elements ( 10   a ) formed on the side of one surface (front surface) of an insulative substrate ( 11 ) composed of a glass substrate. Each of electron source elements ( 10   a ) includes a lower electrode ( 12 ), a buffer layer ( 14 ) composed of an amorphous silicon layer formed on the lower electrode ( 12 ), a polycrystalline silicon layer ( 3 ) formed on the buffer layer ( 14 ), a strong-field drift layer ( 6 ) formed on the polycrystalline silicon layer ( 3 ), and a surface electrode ( 7 ) formed on the strong-field drift layer ( 6 ). The field emission-type electron source can achieved reduced in-plain variation in electron emission characteristics.

TECHNICAL FIELD

The present invention relates to a field emission-type electron sourcefor emitting electron beams by means of the field emission phenomenon,and a method of producing such a field emission-type electron source.

BACKGROUND ART

As one type of electron devices utilizing nanocrystalline silicon(nano-order silicon nanocrystal), there has heretofore been known afield emission-type electron source as shown in FIGS. 17 and 18 (see,for example, Japanese Patent Publication Nos. 2987140 and 3112456).

The field emission-type electron source 10′ (hereinafter referred to as“electron source” for brevity) illustrated in FIG. 17 includes an n-typesilicon substrate 1 as a conductive substrate, a strong-field driftlayer (hereinafter referred to as “drift layer” for brevity) 6 composedof an oxidized porous silicon layer and formed on the side of a mainsurface of the n-type silicon substrate 1, a surface electrode 7composed of a metal thin film (e.g. gold thin film) and formed on thefront surface of the drift layer 6, and an ohmic electrode 2 formed onthe back surface of the n-type silicon substrate 1. The combination ofthe n-type silicon substrate 1 and the ohmic electrode 2 serves as alower electrode 12. In the electron source 10′ illustrated in FIG. 17, anon-doped polycrystalline silicon layer 3 is interposed between then-type silicon substrate 1 and the drift layer 6 to make up an electrontransit section in combination with the drift layer 6. In thisconnection, there has also been known another electron source having anelectron transit section composed only of the drift layer 6 without anypolycrystalline silicon layer 3 interposed between the n-type siliconsubstrate 1 and the drift layer 6.

The electron source 10′ illustrated in FIG. 17 is operable to emitelectrons, for example, according to the following process. A collectorelectrode 21 is first arranged at a position opposed to the surfaceelectrode 7. The space formed between the surface electrode 7 and thecollector electrode 21 is kept in vacuum. Then, a DC voltage Vps isapplied between the surface electrode 7 and the lower electrode 12 insuch a manner that the surface electrode 7 has a higher potential thanthat of the lower electrode 12. Simultaneously, a DC voltage Vc isapplied between the collector electrode 21 and the surface electrode 7in such a manner that the collector electrode 21 has a higher potentialthan that of the surface electrode 7. The DC voltage Vps can be set atan appropriate value to allow electrons injected from the lowerelectrode 12 into the drift layer 6 to drift around the drift layer 6and then run out through the surface electrode 7 (one-dot chain lines inFIG. 17 indicate the flows of the electrons e⁻ emitted through thesurface electrode 7). The thickness of the surface electrode 7 is set inthe range of about 10 to 15 nm.

While the lower electrode 12 in the electron source 10′ illustrated inFIG. 17 is composed of the n-type silicon substrate 1 and the ohmicelectrode 2, it may be substituted with a combination of an insulativesubstrate 11 composed of a glass substrate having an insulationperformance, and a metal thin film formed on one of the surfaces of theinsulative substrate 11, as in another conventional electron source 10″illustrated FIG. 18. In FIG. 18, the same component or element as thatof the electron source 10′ illustrated in FIG. 17 is defined by the samereference numeral or code. The electron source 10″ is operable to emitelectrons according to the same process as that in the electron source10′ illustrated in FIG. 17. Electrons getting through to the frontsurface of the drift layer 6 are considered to be hot electrons. Thus,such electrons can readily tunnels through the surface electrode 7 andrun out into the vacuum space.

Generally, in the electron sources 10′, 10″, a current flowing betweenthe surface electrode 7 and the lower electrode 12 is termed as “diodecurrent Ips”, and a current flowing between the collector electrode 21and the surface electrode 7 is termed as “emission current (emissionelectron current) Ie”. An electron emission efficiency [(Ie/Ips)×100(%)]in the electron sources 10′, 10″ is enhanced as the ratio (Ie/Ips) ofthe emission current Ie to the diode current is increased. Each of theelectron sources 10′, 10″ is operable to emit electrons even if the DCvoltage Vps to be applied between the surface electrode 7 and the lowerelectrode 12 is set at a low value in the range of about 10 to 20 V. Theemission current Ie is increased as the DC voltage Vps is set at ahigher value.

The electron source 10″ illustrated in FIG. 18 is produced, for example,by the following steps. As shown in FIG. 19A, a lower electrode 12 isfirst formed on one main surface (hereinafter referred to as “frontsurface”) of the insulative substrate 11 through a sputtering process orany other suitable process. Subsequently, a non-doped polycrystallinesilicon layer 3 is formed on the front surface of the lower electrode 12through a plasma CVD process or any other suitable process, at asubstrate temperature of 400° C. or more.

Then, as shown in FIG. 19B, the polycrystalline silicon layer 3 isanodized up to a given depth thereof to form a porous polycrystallinesilicon layer 4′. The porous polycrystalline silicon layer 4′ includes aplurality of polycrystalline silicon grains, and a number ofnanometer-order silicon nanocrystals. Subsequently, as shown in FIG.19C, the porous polycrystalline silicon layer 4′ is oxidized through arapid heating process or an electrochemical oxidation process to form adrift layer 6. Then, as shown in FIG. 19D, a surface electrode 7 isformed on the front surface of the drift layer 6 through a vapordeposition process or any other suitable process.

As shown in FIG. 20, the electron source 10″ illustrated in FIG. 18 isused, for example, as an electron source of a display. In a displayillustrated in FIG. 20, a faceplate 50 composed of a flat-plate-shapedglass substrate is set at a position opposed to the electron source 10″.The surface of the faceplate 50 opposed to the electron source 10″ isformed with a collector electrode (hereinafter referred to as “anodeelectrode”) 21 composed of a transparent conductive film (e.g. ITOfilm). The surface of the anode electrode 21 opposed to the electronsource 10″ is provided with fluorescent materials formed in units ofpixels, and block stripes made of black material and formed between thefluorescent materials. Each of the fluorescent materials applied ontothe surface of the anode electrode 21 opposed to the electron source 10″can give out a visible light in response to electrons emitted from theelectron source 10″. The electrons emitted from the electron source 10″are accelerated by a certain voltage applied to the anode electrode 21,and brought into collision with the fluorescent materials in the form ofhighly energized electrons. The fluorescent materials used herein canexhibit luminescent colors R (red), G (green) and B (blue),respectively. The faceplate 50 is spaced apart from the electron source10″ by a rectangular frame (not shown). The space formed between thefaceplate 50 and the electron source 10″ are hermetically sealed andkept in vacuum.

The electron source 10″ illustrated in FIG. 20 includes an insulativesubstrate 11 composed of a glass substrate having an insulationperformance, a plurality of lower electrodes 12 arranged in parallelwith each other on one surface of the insulative substrate 11, aplurality of polycrystalline silicon layers 3 each formed to besuperimposed on the corresponding lower electrode 12, and a plurality ofdrift layers 6 each composed of oxidized porous polycrystalline siliconlayers and each formed to be superimposed on the correspondingpolycrystalline silicon layer. The electron source 10″ further includesa plurality of isolating layers 16 composed of a polycrystalline siliconlayer and disposed to fill in the respective spaces between the adjacentdrift layers 6, between the adjacent polycrystalline silicon layers 3and between the adjacent lower electrodes 12, and a plurality of surfaceelectrodes 7 arranged in parallel with each other on the drift layers 6and the isolating layers 16 to extend across the drift layers 6 and theisolating layers 16 in a direction orthogonal to the longitudinaldirection of the lower electrodes 12.

In the electron source 10″ illustrated in FIG. 20, the combination ofthe drift layers 6, the polycrystalline silicon layers 3 and theisolating layers 16 serves as an electron transit section 5. As shown inFIG. 21, the electron transit section 5 is sandwiched between theplurality of lower electrodes 12 arranged in parallel with each other onthe one surface of the insulative substrate 11, and the plurality of thesurface electrodes 7 arranged in parallel with each other in the planeparallel to the one surface of the insulative substrate 11 to extend ina direction orthogonal to the longitudinal direction of the lowerelectrodes 12. In this connection, there has also been known anotherelectron source having an electron transit section 5 comprised only ofthe drift layers 6 and the isolating layers 16 without anypolycrystalline silicon layer 3 interposed between the drift layer 6 andthe lower electrode 12.

In this electron source 10″, the drift layers 6 are partly sandwiched bythe respective regions corresponding to the cross points between theplurality of lower electrodes 12 arranged in parallel with each other onthe one surface of the insulative substrate 11, and the plurality of thesurface electrodes 7 arranged in parallel with each other to extend in adirection orthogonal to the longitudinal direction of the lowerelectrodes 12. Thus, it can be designed to appropriately select a targetpair of the surface electrode 7 and the lower electrode 12 and apply acertain voltage between the selected pair so as to act a strong electricfield on the region corresponding to the cross point between theselected pair of the surface electrode 7 and the lower electrode 12 toallow electrons to be emitted from the region. That is, a plurality ofelectron source elements 10 a each composed of the lower electrode 12,the polycrystalline silicon layer 3, the drift layer 6 and the surfaceelectrode 7 are formed, respectively, at the cross points of a matrix(lattice) composed of the plurality of lower electrodes 12 and theplurality of surface electrodes 7. Thus, electrons can be emitted fromany desired electron source element 10 a by applying a certain voltageto the corresponding pair of the surface electrode 7 and the lowerelectrode 12. The electron source elements 10 a are formed in one-to-onecorrespondence with the pixels.

The drift layers 6 in the electron source 10″ illustrated in FIG. 20 areprepared according to the following process. A plurality of lowerelectrodes 12 are first formed on one surface of an insulative substrate11. Subsequently, a non-doped polycrystalline silicon 3 is formed on thewhole area of the one surface of the insulative substrate 11 through aplasma CVD process, a low-pressure CVD process or any other suitableprocess at a substrate temperature of 400° C. or more (e.g. 400° C. to600° C.). Then, portions of the polycrystalline silicon layer 3superimposed on the lower electrodes 12 are anodized in an electrolytecontaining a hydrofluoric solution to form a plurality ofpolycrystalline silicon layers. Each of the polycrystalline siliconlayers includes a plurality of porous polycrystalline silicon grains anda number of nanometer-order silicon nanocrystals. Then, the porouspolycrystalline silicon layers are oxidized through a rapid heatingprocess or electrochemical oxidation process to form a plurality ofdrift layers 6. Each of the drift layers 6 includes a plurality ofpolycrystalline silicon grains each having a surface formed with a thinsilicon oxide film, and a number of nanometer-order silicon nanocrystalseach having a surface formed with a silicon oxide film.

As described above, the production process of the electron source 10″illustrated in FIG. 20 comprises the steps of forming the lowerelectrodes 12 on the front surface of the insulative substrate 11,forming the non-doped polycrystalline silicon 3 on the whole area of thefront surface of the insulative substrate 11, anodizing the portions ofthe polycrystalline silicon layer 3 superimposed on the lower electrodes12 to form the porous polycrystalline silicon layers, and oxidizing theporous polycrystalline silicon layers to form the drift layers 6.

That is, in the production process of the electron source 10″illustrated in FIG. 20, the drift layers 6 are formed base on thepolycrystalline silicon layer 3 formed on the lower electrode 12. Inthis process, if some defect, such pinholes, is generated during thecourse of forming the polycrystalline silicon layer 3, it will be likelyto cause a defect of the drift layers 6. This causes the in-planenonuniformity of the electric field applied to the drift layer, andincreased in-plane variation in electron emission characteristic.Consequently, a display is involved in problems of increased unevennessof brightness, and shortened durability due to accelerated deteriorationin a portion of the drift layers 6 subject to strong field intensity.Further, due to the defect of the drift layers 6, the electron source10″ illustrated in FIG. 20 has a problem of increased variation inelectron emission characteristic between production lots.

Similarly, in the electron source 10″ illustrated in FIG. 18, somedefect such pinholes generated during the course of forming thepolycrystalline silicon layer 3 causes a defect of the drift layer 6.This causes a problem of increased variation in electron emissioncharacteristic between production lots, or increased in-plane variationin electron emission characteristic of an electron source having anenlarged area. Further, the electron source 10″ also has a problem ofshortened durability due to accelerated deterioration in a portion ofthe drift layer 6 subject to strong field intensity

DISCLOSURE OF INVENTION

In view of the above problems, it is therefore an object of the presentinvention to provide an electron source having reduced in-planevariation in electron emission characteristic as compared to theconventional electron sources, and to provide a method of producing suchan electron source.

In order to achieve the above-mentioned object, according the presentinvention, there is provided an electron source (field emission-typeelectron source) which includes an insulative substrate, and an electronsource element formed on the side of one surface (front surface) of theinsulative substrate. This electron source element has a lowerelectrode, a surface electrode, and a drift layer (strong-field driftlayer) composed of polycrystalline silicon. The drift layer is disposedbetween the lower and surface electrodes. The strong-field drift layerallows electrons to pass therethrough according to an electric fieldgenerated when a certain voltage is applied to the lower and surfaceelectrodes in such a manner that the surface electrode has a higherpotential than that of the lower electrode. Further, a buffer layerhaving an electrical resistance greater than that of the polycrystallinesilicon is provided between the drift layer and the lower layer.

According to this electron source, defects otherwise generated in thedrift layer can be minimized to achieve the in-plane uniformity of theelectric field applied to the drift layer. Thus, the in-plane variationin electron emission characteristic can be reduced as compared to theconventional electron sources.

In the electron source according to the present invention, the bufferlayer may include (or be composed of) an amorphous layer. This bufferlayer can be readily formed at a relatively low temperature. Inparticular, if the amorphous layer is an amorphous silicon layer, it canbe formed through a commonly used semiconductor production process.

In the electron source according to the present invention, a pluralnumber of the electron source elements may be formed on the side of thefront surface of the insulative substrate. Further, the insulativesubstrate may include (or be composed of) a glass substrate allowinginfrared rays to transmit therethrough. The buffer layer may include (orbe composed of) a portion of a film which is made of a material capableof absorbing infrared rays and formed to cover the whole area on theside of the front surface of the insulative substrate before theformation of the strong-field drift layer. According to this electronsource, when the insulative substrate is heated from the side of anothersurface (back surface) opposite to the front surface to form the driftlayer, the temperature distribution on the side of the front surface canbe uniformed irrespective of the pattern of the lower electrode. Inaddition, as comparted to an electron source in which a film serving asthe buffer layer is formed only in the region where it is superimposedon the lower electrode, the in-plane variation in properties of thedrift layer can be minimized to reduce the in-plane variation inelectron emission characteristic.

In one specific embodiment of the present invention, the strong-fielddrift layer of the electron source may include (or be composed of)anodized porous polycrystalline silicon. Further, this strong-fielddrift layer may include a plurality of columnar semiconductor crystalseach formed along the thickness direction of the lower electrode, and anumber of nanometer-order semiconductor nanocrystals residing betweenthe semiconductor crystals and each having a surface formed with aninsulating film which has a thickness less than the grain size of thesemiconductor nanocrystal. According to this electron source, the vacuumdependence during electron emission can be reduced. In addition, a partof heat generated in the drift layer can be released through thecolumnar semiconductor crystals. Thus, this electron source can stablyemit electrons without a popping phenomenon otherwise caused duringelectron emission.

The present invention also provides a method of producing the aboveelectron source. This method includes forming the lower electrode on theside of the front surface of the insulative substrate, and then formingthe buffer layer on the lower electrode before forming the strong-fielddrift layer.

This production method can minimize occurrence of defects otherwisegenerated in the drift layer to enhance the properties of the driftlayer, as compared to the conventional method in which the drift layeris formed directly on the lower electrode. Thus, the method can providean electron source having low in-plane variation in electron emissioncharacteristic. In addition, the method can reduce the variation inelectron emission characteristic between production lots.

Further, the present invention provides a method of producing theelectron source according to the above specific embodiment. Thisproduction method includes a lower-electrode forming step of forming thelower electrode on the side of the front surface of the insulativesubstrate, a first film-forming step of forming the buffer layer on theside of the front surface of the insulative substrate after thelower-electrode forming step, a second film-forming step of forming apolycrystalline semiconductor layer on the surface of the buffer layer,a nanocrystallization step of nanocrystallizing at least a portion ofthe polycrystalline semiconductor layer through an anodizing process toform the semiconductor nanocrystals, and an insulating-film forming stepof forming the insulating film on the surface of each of thesemiconductor nanocrystals. According to this production method, theoccurrence of defects otherwise generated in the polycrystalline siliconlayer can be minimized as compared to the combinational method in whichthe polycrystalline semiconductor layer is formed directly on the lowerelectrode.

In the above production method, the second film-forming step may beperformed after the first film-forming step without exposing the surfaceof the buffer layer to the atmosphere. This method can prevent a barrierlayer composed of an oxide film from being formed between the bufferlayer and the polycrystalline semiconductor layer to avoid deteriorationin electron emission characteristic due to the barrier layer.

In the above production method, a plasma CVD process may be used as afilm-forming process in each of the first and second film-forming steps.In this case, when the first film-forming step is shifted to the secondfilm-forming step, a discharge power or discharge pressure for theplasma CVD process may be changed from a first condition for forming thebuffer layer to a second condition for forming the polycrystallinesemiconductor layer. This method can simplify the film-forming processas compared to a conventional method in which a plurality of processparameters including a discharge power or discharge pressure.

In the above production method, a plasma CVD process or catalytic CVDprocess may be used as a film-forming process in each of the first andsecond film-forming steps. In this case, when the first film-formingstep is shifted to the second film-forming step, the partial pressureratio or kind of source gases for the plasma CVD process or catalyticCVD process is changed from a first condition for forming the bufferlayer to a second condition for forming the polycrystallinesemiconductor layer. This method can simplify the film-forming processas compared to a conventional method in which a plurality of processparameters including the partial pressure ratio or kind of source gases.

The production methods according to the present invention may furtherincludes between the first and second film-forming steps a pre-growthtreatment step of subjecting the surface of the buffer layer to atreatment for facilitating the creation of a crystal nucleus in theinitial stage of the second film-forming step. This method canfacilitate crystal growth in the polycrystalline semiconductor layerwhen the polycrystalline semiconductor layer is formed in the secondfilm-forming step, to provide enhanced electron emission characteristicand durability of the electron source.

Further, the pre-growth treatment step may be the step of subjecting thesurface of the buffer layer to a plasma treatment. When a film-formingapparatus utilizing plasma, such as a plasma CVD apparatus, is employedin the second film-forming step, this pre-growth treatment step can beperformed in the same chamber as that for the second film-forming step.Thus, the pre-growth treatment step and the second film-forming step canbe successively performed to provide a reduced process time.

The pre-growth treatment step may be the step of subjecting the surfaceof the buffer layer to a hydrogen plasma treatment. In this case, thesecond film-forming step may include forming a polycrystalline siliconlayer serving as the polycrystalline semiconductor layer through aplasma CVD process using a source gas including at least a silane-basedgas. This pre-growth treatment step can be performed in the same chamberas that for the second film-forming step. Thus, the pre-growth treatmentstep and the second film-forming step can be successively performed toprovide a reduced process time. When source gases including asilane-based gas and a hydrogen gas are used in the second film-formingstep, the pre-growth treatment step may be performed by using thehydrogen gas as one of the source gases, which is introduced into thechamber through a pipe for the hydrogen gas. This can eliminate the needfor particular modifications of an apparatus for use in the plasma CVDprocess.

Alternatively, the pre-growth treatment step may be the step ofsubjecting the surface of the buffer layer to an argon plasma treatment.When a film-forming apparatus using plasma, such as a plasma CVDapparatus, is employed in the second film-forming step, this pre-growthtreatment step can be performed in the same chamber as that for thesecond film-forming step. Thus, the pre-growth treatment step and thesecond film-forming step can be successively performed to provide areduced process time and further facilitate crystallization in thepolycrystalline semiconductor layer.

Alternatively, the pre-growth treatment step may be the step of forminga layer including a number of silicon nanocrystals, on the surface ofthe buffer layer. This pre-growth treatment can facilitatecrystallization in the polycrystalline semiconductor layer without anyplasma treatment.

BRIEF DESCRIPTION OF DRAWINGS

Other features and advantages of the present invention will be apparentfrom the accompanying drawings and from the detailed description. In theaccompanying drawings, common components or elements are defined by thesame reference numeral or marks.

FIG. 1 is a partially broken perspective view of an electron source(field emission-type electron source) according to one embodiment of thepresent invention.

FIG. 2 is a schematic fragmentary enlarged sectional view of theelectron source in FIG. 1.

FIG. 3 is an explanatory diagram of the operation of the electron sourcein FIG. 1.

FIG. 4 is a schematic fragmentary block diagram of an image display unitusing the electron source in FIG. 1.

FIG. 5 is an explanatory diagram of a driving method for the electronsource in FIG. 1.

FIGS. 6A to 6D are schematic sectional views showing intermediate andfinal products in a production method for an electron source accordingto the present invention.

FIG. 7 is an explanatory diagram of the operation of an electron sourceaccording to the present invention.

FIG. 8 is a graph showing an electron emission characteristic of anelectron source according to the present invention.

FIG. 9 is a graph showing an electron emission characteristic of anelectron source as a comparative example.

FIG. 10A is a diagram showing a luminescence pattern of a display unitusing an electron source as a comparative example.

FIG. 10B is a diagram showing a luminescence pattern of a display unitusing an electron source according to the present invention.

FIG. 11 is a graph showing an electron emission characteristic ofanother electron source according to the present invention.

FIG. 12 is a graph showing an electron emission characteristic ofanother electron source as a comparative example.

FIG. 13 is a graph showing an electron emission characteristic of stillanother electron source according to the present invention.

FIG. 14 is a graph showing an electron emission characteristic of stillanother electron source as a comparative example.

FIG. 15 is an explanatory diagram of a production method for an electronsource according to the present invention.

FIG. 16 is an explanatory diagram of a production method for an electronsource, for the purpose of comparison.

FIG. 17 is an explanatory diagram of the operation of a conventionalelectron source.

FIG. 18 is an explanatory diagram of the operation of anotherconventional electron source.

FIGS. 19A to 19D are schematic sectional views showing intermediate andfinal products in a production method for a conventional electronsource.

FIG. 20 is a schematic perspective view showing a display using theelectron source in FIG. 17.

FIG. 21 is a schematic perspective view showing the electron source ofthe display in FIG. 20.

BEST MODE FOR CARRYING OUT THE INVENTION

This application is based upon and claims the benefit of priority fromthe prior Japanese Patent Application No. 2002-381944 filed in Japan,the entire contents of which are incorporated herein by reference.

With reference to the accompanying drawings, embodiments of the presentinvention will now be specifically described.

As shown in FIG. 1, an electron source (field emission-type electronsource) 10 according to the embodiment includes an insulative substrate11 composed of a glass substrate having an insulation performance, aplurality of lower electrodes 12 arranged in parallel with each other onthe side of one main (front surface) of the insulative substrate 11, aplurality of surface electrodes 7 arranged in parallel with each otherin a plane parallel to the front surface of the insulative substrate 11to extend in a direction orthogonal to the lower electrodes 12, and anelectron transit section provided on the side of the front surface ofthe insulative substrate 11. The electron transit section includes aplurality of buffer layer 14 composed of an non-doped amorphous siliconlayer and each formed to be superimposed on the corresponding lowerelectrode 12, a plurality of polycrystalline silicon layers 3 eachformed to be superimposed on the corresponding buffer layer 14, aplurality of drift layers (strong-field drift layers) 6 each formed tobe superimposed on the corresponding polycrystalline silicon layer 3,and a plurality of isolating layers 16. The isolating layers 16 aredisposed to fill in the respective spaces between the adjacent driftlayers 6, between the adjacent polycrystalline silicon layers 3 andbetween the adjacent non-doped amorphous silicon layers formed as thebuffer layer 14. Each of the isolating layers 16 is composed of anon-doped polycrystalline silicon layer formed together with thepolycrystalline silicon layer 3 and a non-doped amorphous silicon layerformed together with the buffer layer 14.

The lower electrodes 12 are formed by patterning a single-layer thinfilm made of metal (e.g. metal, such as W, Mo, Cr, Ti, Ta, Ni, Al, Cu,Au or Pt, alloy thereof, or intermetallic compound such as silicide).Alternatively, the lower electrodes 12 may be formed by patterning amulti-layer thin film made of metal. Each of the lower electrodes 12 hasa thickness of about 250 to 300 nm.

The surface electrodes 7 are made of a material (e.g. gold) having asmall work function. However, the material of the surface electrodes 7is not limited to gold. Each of the surface electrodes 7 may be eitherone of single-layer and multi-layer structures. The thickness of thesurface electrode 7 may be set at any suitable value, for example about10 to 15 nm, which allows electrons from the drift layer 6 to tunneltherethrough. Each of the lower electrodes 12 and the surface electrodes7 is formed in a strip shape. Each of the surface electrodes 7 is partlyopposed to the lower electrodes 12. Each of the lower electrodes 12 haslongitudinally opposite ends each of which is formed with a pad 28. Eachof the surface electrodes 7 has longitudinally opposite ends each ofwhich is formed with a pad 27.

As with the conventional electron source 10″ illustrated in FIG. 20, inthe electron source 10 according to this embodiment, the drift layers 6are partly sandwiched by the respective regions corresponding to thecross points between the plurality of lower electrodes 12 arranged inparallel with each other on the side of the front surface of theinsulative substrate 11, and the plurality of the surface electrodes 7arranged in parallel with each other to extend in a direction orthogonalto the longitudinal direction of the lower electrodes 12. Thus, it canbe designed to appropriately select a target pair of the surfaceelectrode 7 and the lower electrode 12 and apply a certain voltagebetween the selected pair so as to act a strong electric field on theregion corresponding to the cross point between the selected pair of thesurface electrode 7 and the lower electrode 12 to allow electrons to beemitted from the region. That is, a plurality of electron sourceelements 10 a each composed of the lower electrode 12, the buffer layer14, the polycrystalline silicon layer 3, the drift layer 6 and thesurface electrode 7 are formed, respectively, at the cross points of amatrix (lattice) composed of the plurality of surface electrodes 7 andthe plurality of lower electrodes 12. Thus, electrons can be emittedfrom any desired electron source element 10 a by applying a certainvoltage to the corresponding pair of the surface electrode 7 and thelower electrode 12. For this reason, each of the surface electrodes 7 isnot necessarily formed in a strip shape. For example, the surfaceelectrodes may be formed to cover only the regions corresponding to theelectron source elements 10 a, and the surface electrode 7 arrangedalong a direction orthogonal to the longitudinal direction of the lowerelectrodes 12 may be electrically connected with each other by a buselectrode having a low resistance.

The drift layers 6 are formed through after-mentionednanocrystallization and oxidation processes. As shown in FIG. 2, each ofthe drift layers 6 includes a plurality of columnar polycrystallinesilicon grains (semiconductor crystals) 51 extending in parallel witheach other from the side of the front surface of the lower electrode 12and each having a surface formed with a thin silicon oxide film 52, anda number of nanometer-order silicon nanocrystals (semiconductornanocrystals) 63 residing between the grains 51 and each having asurface formed with a silicon oxide film (insulating film) 64 which hasa thickness less than the grain size of the semiconductor nanocrystal.Each of the grains 51 extends along the thickness direction of the lowerelectrodes 12 (or extends along the thickness direction of theinsulative substrate 11).

Each of the electron source elements 10 a in this embodiment is operableto emit electrons, for example, according to the following process. Asshown in FIG. 3, a collector electrode 21 is first arranged at aposition opposed to the surface electrode 7. The space formed betweenthe surface electrode 7 and the collector electrode 21 is kept invacuum. Then, a DC voltage is applied from a driveling power supply Vato between the surface electrode 7 and the lower electrode 12 in such amanner that the surface electrode 7 has a higher potential than that ofthe lower electrode 12. Simultaneously, a DC voltage Vc is appliedbetween the collector electrode 21 and the surface electrode 7 in such amanner that the collector electrode 21 has a higher potential than thatof the surface electrode 7. The DC voltage Vps can be set at anappropriate value to allow electrons injected from the lower electrode12 into the drift layer 6 to drift around the drift layer 6 and then runout through the surface electrode 7.

The above electron emission in the electron source element 10 a would becaused based on the following model.

A driving voltage is applied from the driving power supply Va to betweenthe surface electrode 7 and the lower electrode 2 to provide a higherpotential to the surface electrode 7. Through this operation, electronse⁻ are injected from the lower electrode 12 into the drift layer 6.Electric field concurrently applied to the drift layer 6 mostly acts onthe silicon oxide films 64. Thus, the electrons e⁻ injected into thedrift layer 6 is accelerated by the strong electric field acting on thesilicon oxide films 64. After drifting in the direction of the arrows inFIG. 3, the electrons e⁻ tunnel through the surface electrode 7 and thenrun out into the vacuum space. Within the drift layer, the electrons e⁻injected from the lower electrode 12 are almost never scattered by thesilicon nanocrystals 63. Thus, the electrons accelerated by the electricfield acting on the silicon oxide films 64 can drift and run out throughthe surface electrode 7. In addition, heat generated in the drift layer6 is released through the grains 51. Thus, the electrons can be emittedwithout occurrence of a hopping phenomenon during the electron emission.The electrons getting through to the front surface of the drift layer 6are considered to be hot electrons. Thus, the electrons can readilytunnels through the surface electrode 7 and run out into the vacuumspace.

In the electron source 10 according to this embodiment, CS77 (trade nameof a glass substrate available from Saint-Gobain Co.) which is one ofhigh-strain point glass substrates for use in PDP is used as theinsulative substrate 11 (glass substrate). In this case, the insulativesubstrate 11 has a thermal expansion coefficient greater than that ofsilicon. Therefore, an anti-peeling layer 13 composed of a non-dopedpolycrystalline silicon layer is interposed between the lower electrode12 and the insulative substrate 11 to prevent the electron transitsection 5 from peeling from the lower electrode 12.

The electron source 10 according to this embodiment is used, forexample, in a multicolor image display unit. In this case, the electronsource 10 is driven by a drive circuit 30 as shown in FIG. 4. The drivecircuit 30 includes an X controller 33 which controls the potential ofthe surface electrodes 7 belonging to each of X electrode groupscomposed of the plurality of the surface electrodes 7, a Y controller 34which controls the potential of the lower electrodes 12 belonging toeach of Y electrode groups composed of the plurality of the lowerelectrodes 12, a signal processor 31 which converts an input imagesignal into drive signals for driving the electron source 10 with amatrix structure, and a biasing (or driving) signal controller 32 whichissues instructions to the X controller 33 and the Y controller 34 inresponse to the drive signals converted by the signal processor 31. Aswith the conventional electron source 10″ illustrated in FIG. 20, theelectron source elements 10 a are formed in one-to-one correspondencewith pixels which are provided in a glass faceplate 50 (see FIG. 20) tobe arranged at a position opposed to the electron source 10 andcomposed, respectively, of fluorescent materials exhibiting colors R, Gand B.

As shown in FIG. 5, in the drive circuit 30 for driving the electronsource 10 according to this embodiment, a single-pulsed forward-biasvoltage V1 is applied between the surface electrode 7 and the lowerelectrode 12 of the selected electron source element 10 a. Subsequently,a single-pulsed reverse-bias voltage V2 is applied between the surfaceelectrode 7 and the lower electrode 12 of the same electron sourceelement 10 a. For this purpose, the drive circuit 30 is provided with areverse bias controller 35 which controls the reverse bias voltage. Thereverse bias controller 35 is operable to detect a reverse currentflowing through the above electron source element 10 a. Then, thereverse bias controller 35 is operable to control the reverse biasvoltage to be applied between the surface electrode 7 and the lowerelectrode 12 so as to allow the reverse bias voltage to fall within adesired range (for example, to be stabilized at a specified currentvalue defined by a reverse current value at the time the drive of theelectron source element 10 a is initiated).

With reference to FIGS. 6A to 6D, a production method for the electronsource will be described below. Each of FIGS. 6A to 6D shows a verticalsection corresponding to only one of the electron source elements 10 a.

In order to form the anti-peeling layers 13, a non-doped polycrystallinesilicon layer having a given thickness (e.g. 100 nm) is first formed onthe front surface of the insulative substrate 11 having a giventhickness (e.g. 2.8 mm) through a plasma CVD process at a give processtemperature (e.g. 450° C.). Subsequently, in order to form the lowerelectrodes 12, a metal thin film (e.g. tungsten film) having a giventhickness (e.g. 250 nm) is formed on the polycrystalline silicon layerthrough a sputtering process. Then, a photoresist material is applied onthe metal thin film to form a photoresist layer thereon. Further, inorder to leave the regions of the metal thin film corresponding to thelower electrodes 12, the photoresist layer is patterned usinglithography. Then, the metal thin film and the polycrystalline siliconlayer are pattered through a reactive ion etch process using thepatterned photoresist layers as a mask. Through the above step, theplurality of lower electrodes 12 each composed of a portion of the metalthin film, and the plurality of anti-peeling layers 13 each composed ofa portion of the polycrystalline silicon layers are formed(lower-electrode forming step).

After removing the photoresist layers, an amorphous silicon layer havinga given thickness (e.g. 80 nm) serving as a buffer layer 14 is formed tocover the whole area on the side of the above one surface or frontsurface of the insulative substrate 11 the through a plasma CVD process(first film-forming step). Subsequently, a non-doped polycrystallinesilicon layer 3 (semiconductor layer) having a given thickness (e.g. 1.5μm) is formed on the buffer layer 14 through a plasma CVD process at agiven process temperature (e.g. 450° C.) (second film-forming step)Through the above step, an intermediate product having the structureillustrated in FIG. 6A can be obtained.

After the formation of the non-doped polycrystalline silicon layer 3,the intermediate product illustrated in FIG. 6A is subject to ananocrystallization process (nanocrystallization step). Through thisstep, a composite nanocrystal layer (herein after referred to as “firstcomposite nanocrystal layer”) 4 composed of polycrystalline siliconincluding a mixture of a number of grains 51 (see FIG. 2) and a numberof silicon nanocrystals 63 (see FIG. 2) is formed in the regions to beformed as the drift layers 6. Consequently, an intermediate producthaving the structure illustrated in FIG. 6B can be obtained.

The nanocrystallization process is performed using an electrolyteprepared by mixing 55 wt % of hydrofluoric solution and ethanol at amixing ratio of 1:1. The intermediate product illustrated in FIG. 6A isimmersed in the electrolyte while positioning the lower electrodes 12used as anode and platinum electrodes used as cathode on the both sidesof the polycrystalline silicon layer 3. Then, a constant current (e.g.current with a current density of 12 mA/cm²) is supplied between theanode and cathode for a given time-period (e.g. 10 seconds) whileirradiating the main surface of the polycrystalline silicon layer 3 withlight from a light source composed of a 500 W tungsten lamp. Throughthis step, the first composite nanocrystal layer including the grains 51and the silicon nanocrystals 63 are formed in each of the regions of thepolycrystalline silicon layer 3 superimposed on the lower electrodes 12.

After the completion of the nanocrystallization process, theintermediate product illustrated in FIG. 6B is subjected to an oxidationprocess (insurating-film forming process) so as to oxidize the firstcomposite nanocrystal layers 4. Through this step, the drift layer 6composed of a composite nanocrystal layer (hereinafter referred to as“second composite nanocrystal layer) having the structure illustrated inFIG. 2 is formed in each of the regions of the polycrystalline siliconlayer 3 superimposed on the lower electrodes 12. Consequently, anintermediate product having the structure illustrated in FIG. 6C can beobtained.

The oxidation process is performed using an electrolyte prepared bydissolving 0.04 mol/l of potassium nitrate (dissolved substance) inethylene glycol (organic solvent). The intermediate product illustratedin FIG. 6C is immersed in the electrolyte while positioning the lowerelectrodes 12 used as anode and platinum electrodes used as cathode onthe both sides of each of the first composite nanocrystal layers 4.Then, a constant current (e.g. current with a current density of 0.1mA/cm²) is supplied between the anode and cathode until the voltagebetween the anode and cathode is increased by 20 V to electrochemicallyoxidize the first composite nanocrystal layers 4. Through this step, thedrift layers 6 each composed of the second composite nanocrystal layerincluding the grains 51 covered, respectively, with the silicon oxidefilms 52 and the silicon nanocrystals 63 covered, respectively, with thesilicon oxide film 53 are formed. In the polycrystalline silicon layer3, each of the portions filling between the adjacent drift layers 6serves as an isolating layer 16.

In this embodiment, the region other than the grains 51 and the siliconnanocrystals 63 in each of the first composite nanocrystal layers 4formed through the nanocrystallization process includes is formed as anamorphous region composed of amorphous silicon. The region other thanthe grains 51 with the silicon oxide films 52 and the siliconnanocrystals 63 with the silicon oxide films 64 in each of the driftlayers 6 is formed as an amorphous region 65 composed of amorphoussilicon or partially oxidized amorphous silicon. Otherwise, theamorphous region 65 can be formed as pores, depending on the conditionsof the nanocrystallization process. In this case, each of the firstcomposite nanocrystal layers 4 has the same structure as that of theporous polycrystalline silicon layer 4′ (see FIG. 19).

After the formation of the drift layers 6 and the isolating layers 16,the surface electrodes 7 each composed of a gold thin film is formedthrough a vapor deposition process. Through this step, the electronsource 10 illustrated in FIG. 6D can be obtained.

The electron source 10 (electron source elements 10 a) has the bufferlayer 14 interposed between the drift layer 6 and the lower electrode12. Thus, defects otherwise generated in the drift layer 6 can beminimized to provide enhanced in-plane uniformity in electric filedapplied to the drift layer 6 and reduced variation in in-plane electronemission characteristic, as compared to the conventional electronsources. More specifically, according to the above production method,the risk of generating defects in the non-doped polycrystalline siliconlayer 3 to be formed as the drift layers 6 can be reduced as compared tothe conventional electron sources having no buffer layer 14 on the lowerelectrode 12. As a natural consequence, the risk of generating defectsin the drift layers 6 can also be reduced to provide enhanced propertiesof the drift layers. Thus, this method can provide an electron sourcehaving reduced in-plane variation in electron emission characteristic ascompared to the conventional electron sources. In addition, this methodcan provide reduced variation in electron emission characteristic of theelectron source 10 between production lots.

The above embodiment employs an amorphous layer, such as an amorphoussilicon layer, serving as the buffer layer 14. However, the amorphouslayer generally has a higher electrical resistance than a polycrystallayer such as a polycrystalline silicon layer. For this reason, theelectrical resistance of the buffer layer 14 is increased as thethickness of the buffer layer 14 is increased, resulting in degradationin properties of an electron source. Thus, the thickness of the bufferlayer 14 is desired to be thinner. Specifically, any adverse affect fromthe electrical resistance of the buffer layer 14 can be suppressed bysetting the buffer layer 14 to have a thickness equal to or less thanthat of the polycrystalline silicon layer 3 to be interposed between thebuffer layer 14 and the drift layer 6.

One specific example (hereinafter referred to as “Example 1”) will bedescribed below based on the electron emission characteristic of anelectron source 10 in which the thickness of the buffer layer 14 is 80nm, and each number of the surface electrodes 7 and the lower electrodes12 is four. For ease of explanation, given that the four surfaceelectrodes 7 also serve, respectively, as row-selecting electrodes X1,X2, X3 and X4, and the four lower electrodes 12 also serve,respectively, as column-selecting electrodes Y1, Y2, Y3 and Y4, as shownin FIG. 7. The electron source elements 10 a are fundamentally drivenunder the same condition as that illustrated in FIG. 5, wherein thereverse bias voltage V1 is 18V, the pulse width H1 being 5 ms, thereverse bias voltage V2 being −10V, and the pulse width H2 being 5 ms.

FIG. 8 shows the electron emission characteristic of the electron source10 as Inventive Example 1. FIG. 9 shows the electron emissioncharacteristic of an electron source 10 having no buffer layer 4, as onecomparative example (hereinafter referred to as “Comparative Example1”). In FIGS. 8 and 9, the horizontal and vertical axes represent adriving voltage (bias voltage) and a current density, respectively. InFIGS. 8 and 9, each of four kinds of marks (graphs) having higher valuesin the vertical axis indicates the current density of the diode currentIps (see FIG. 3), and each of four kinds of marks (graphs) having lowervalues in the vertical axis indicates the current density of theemission current Ie (see FIG. 3). The line A indicated by the mark “◯”shows the characteristic of the four electron source elements 10 aassociated with the column-selected electrodes Y1. The line B indicatedby the mark “□” shows the characteristic of the four electron sourceelements 10 a associated with the column-selected electrodes Y2. Theline C indicated by the mark “Δ” shows the characteristic of the fourelectron source elements 10 a associated with the column-selectedelectrodes Y3. The line D indicated by the mark “∇” shows thecharacteristic of the four electron source elements 10 a associated withthe column-selected electrodes Y4. As seen from the comparison betweenFIGS. 8 and 9, the thickness of the buffer layer set at 80 nm has noadverse affect on the I-V characteristic.

FIGS. 10A and 10B show measurement results of the luminescence pattern(electron emission characteristic) of a fluorescent material layer of afaceplate, wherein the faceplate is arranged at a position opposed tothe electron source 10, and the fluorescent material layer is formed onthe surface of the faceplate opposed to the electron source 10. FIG. 10Ashows the luminescence pattern of a display unit using the electronsource of Comparative Example 1 having no buffer layer 14. FIG. 10Bshows the luminescence pattern of a display unit using the electronsource 10 of Inventive Example 1 having the buffer layer 14. As seenfrom the comparison between FIGS. 10A and 10B, Inventive Example 1having the buffer layer 14 has a lower in-plane variation in brightnessthan that of Comparative Example 1 having no buffer layer 14. Thebrightness depends on the level of the emission current Ie. Thus, it isproved that Inventive Example 1 having the buffer layer 14 has a lowerin-plane variation in emission current Ie than that of ComparativeExample 1 having no buffer layer 14. Further, this result shows that thethickness of the buffer layer 14 set at 100 nm can provide sufficientlyenhanced in-plane uniformity in electron emission characteristic. Thus,the thickness of the buffer layer 14 is preferably set in the range of100 to 200 nm.

In the above production method for the electron source, a plasma CVDprocess is used as the film-forming process in the step of forming thebuffer layer 14 (first film-forming step). The plasma CVD process isalso used as the film-forming process in the step of forming thenon-doped polycrystalline silicon layer 3 (second film-forming step).Thus, both the first and second film-forming steps can be performedusing a single or common plasma CVD apparatus. In this case, after thecompletion of the first film-forming step, the second film-forming stepcan be performed without exposing the surface of the buffer layer 14 tothe atmosphere. Thus, the risk of having an oxide film or barrier layerformed between the buffer layer 14 and the polycrystalline silicon layer3 can be eliminated to prevent the electrical resistance of the barrierlayer from adversely affecting on electron emission characteristic. Inaddition, the first and second film-forming steps can be successivelyperformed in a common chamber to provide a reduced process time.

The process parameter of the plasma CVD process used in the first andsecond film-forming steps includes discharge power, discharge pressure,the partial pressure ratio of source gases, the kind of source gas, theflow volume of source gas, and substrate temperature. In the aboveembodiment, the buffer layer 14 to be formed in the first film-formingstep is an amorphous silicon layer, and the polycrystallinesemiconductor layer to be formed in the second film-forming step is anon-doped polycrystalline silicon layer 3. Thus, when the firstfilm-forming step is shifted to the second film-forming step, adischarge power can be changed from a first condition (e.g. 400 W) forforming the buffer layer 14 to a second condition (e.g. 1.8 kW) forforming the polycrystalline silicon layer 3 to provide a simplifiedprocess as compared to a technique of changing a plural number of theprocess parameters.

Similarly, when the first film-forming step is shifted to the secondfilm-forming step, a discharge pressure can be changed from a firstcondition (e.g. 6.7 Pa) for forming the buffer layer 14 to a secondcondition (e.g. 6.7 Pa) for forming the polycrystalline silicon layer 3to simplify the process as compared to a technique of changing aplurality of parameters to provide a simplified process as compared to atechnique of changing a plural number of the process parameters. Whenthe first film-forming step is shifted to the second film-forming step,the partial pressure ratio of a silane-based gas (e.g. SiH₄ gas) to H₂gas which are source gases can be changed from a first condition (e.g.SiH₄:H₂=1:0) for forming the buffer layer 14 to a second condition (e.g.SiH₄:H₂=1:10) for forming the polycrystalline silicon layer 3 tosimplify the process as compared to a technique of changing a pluralityof parameters to provide a simplified process as compared to a techniqueof changing a plural number of the process parameters. When the firstfilm-forming step is shifted to the second film-forming step, the kindof source gas to H₂ gas which are source gases can be changed from afirst condition (e.g. combination of SiH₄ gas and N₂ gas) for formingthe buffer layer 14 to a second condition (e.g. combination of SiH₄ gasand Ar gas) for forming the polycrystalline silicon layer 3 to simplifythe process as compared to a technique of changing a plurality ofparameters to provide a simplified process as compared to a technique ofchanging the process parameter. It is understood that a plural number ofthe process parameters may be changed when the first film-forming stepis shifted to the second film-forming step.

Alternatively, a catalytic CVD process may be used as the film-formingprocess in the first and second film-forming steps. In this case, whenthe first film-forming step is shifted to the second film-forming step,one of the process parameters (e.g. the partial pressure ratio or thekind of source gas) may be changed or the plural number of the processparameters may be changed.

Between the first and second film-forming steps, the above productionmethod may further include a pre-growth treatment step of subjecting thesurface of the buffer layer 14 to a treatment for facilitating thecreation of a crystal nucleus in the initial stage of the secondfilm-forming step. This method can facilitate crystal growth in thepolycrystalline silicon layer 3 when the polycrystalline silicon layeris formed in the second film-forming step, to provide improved filmquality, so that the electron emission characteristic and durability ofthe electron source 10 can be enhanced. As the pre-growth treatmentstep, the step of subjecting the surface of the buffer layer 14 to aplasma treatment may be used. Further, the pre-growth treatment step andthe second film-forming step may be performed using a single or commonplasma CVD apparatus (or performed in a common chamber). In this case,the pre-growth treatment step and the second film-forming step can besuccessively performed to provide a reduced process time.

A hydrogen plasma treatment or an argon plasma treatment may be used asthe plasma treatment. In the hydrogen plasma treatment, when sourcegases including a silane-based gas and a hydrogen gas are used in thesecond film-forming step, the pre-growth treatment step may be performedby using the hydrogen gas as one of the source gases, which isintroduced into the chamber through a pipe for the hydrogen gas. Thiscan eliminate the need for particular modifications of an apparatus foruse in the plasma CVD process.

As compared to the hydrogen plasma treatment, the argon plasma treatmentallows the crystallization in the polycrystalline silicon layer 3 to befurther facilitated. Alternatively, the pre-growth treatment step may bethe step of forming a layer including a number of silicon nanocrystals,on the surface of the buffer layer 14. This pre-growth treatment canfacilitate crystallization in the polycrystalline silicon layer 3without any plasma treatment.

FIGS. 11 and 13 show the aging in electron emission characteristic of anelectron source 10, as another specific example (hereinafter referred toas “Inventive Example 2”) produced by performing the pre-growthtreatment. FIGS. 12 and 14 show the aging in electron emissioncharacteristic of an electron source 10, as another specific example(hereinafter referred to as “Comparative Example 2”) produced withoutany pre-growth treatment.

In FIGS. 11 and 12, the horizontal and vertical axes represent a drivingvoltage (bias voltage) and a current density, respectively. In FIGS. 11and 12, each of four kinds of marks (graphs) having higher currentdensity values in the vertical axis indicates the current density of thediode current Ips (see FIG. 3), and each of four kinds of marks (graphs)having lower current density values in the vertical axis indicates thecurrent density of the emission current Ie (see FIG. 3). The line Aindicated by the mark “◯” shows the characteristic of the four electronsource elements 10 a associated with the column-selected electrodes Y1.The line B indicated by the mark “□” shows the characteristic of thefour electron source elements 10 a associated with the column-selectedelectrodes Y2. The line C indicated by the mark “Δ” shows thecharacteristic of the four electron source elements 10 a associated withthe column-selected electrodes Y3. The line D indicated by the mark “∇”shows the characteristic of the four electron source elements 10 aassociated with the column-selected electrodes Y4.

In FIGS. 13 and 14, the horizontal axis represents a lapsed time fromthe initiation of driving in case of continuous driving. The verticalaxis on the left side represents a current density, and the verticalaxis on the right side represents the electron emission efficiency. InFIGS. 13 and 14, the line α shows the current density of the diodecurrent Ips, the line β showing the current density of the emissioncurrent Ie, and line γ shows an electron emission efficiency. Thetime-period of exposure to hydrogen plasma in the pre-growth treatmentwas 40 minutes. Other conditions of the pre-growth treatment were asubstrate temperature of 400° C., a discharge pressure of 1.3 Pa, and adischarge power of 2 kW.

As seen from the comparison between FIGS. 11 and 12, Inventive Example 2subjected to the pre-growth treatment is more enhanced in I-Vcharacteristic (enhanced in emission current Ie) than that ofComparative Example 2 subjected to no pre-growth treatment. As seen fromthe comparison between FIGS. 13 and 14, Inventive Example 2 subjected tothe pre-growth treatment has more enhanced in emission current Ie andelectron emission efficiency than those of Comparative Example 2subjected to no pre-growth treatment.

In the above embodiment, the anti-peeling layer is interposed betweenthe lower electrode 12 and the insulative substrate 11. Thus, the riskof causing the peeling of layers composed of or to be formed as theelectron transmit section 5 during production process of the electronsource 10 can be reduced as compared to the conventional electronsources to facilitate improvement in process yield, and reduction inproduction cost and cost of the electron source 10. In addition, even inthe electron source as a product, the electron transit section 5 can beprevented from peeling from the lower electrode 12 to achieve enhancedreliability. When a glass substrate having a thermal expansioncoefficient closer to that of silicon than that of a high-strain pointglass substrate is used as the insulative substrate 11, the anti-peelinglayer may be omitted.

When a glass substrate used as the insulative substrate 11 is heatedfrom the side of the surface opposite to the front surface, or the backsurface, of the insulative substrate by using a heater to have a desiredsubstrate temperature, the lower electrodes 12 are heated by infraredrays emitted from the heater. Thus, when the insulative substrate 11 isheated from the side of the back surface thereof with a heater in thesecond film-forming step, the temperature of the electron source havingno buffer layer is locally varied depending on the pitch of the lowerelectrodes 12, as shown in FIG. 16. In this case, the regions where thelower electrodes 12 are arranged at a wide pitch will be insufficientlyheated. Thus, the regions 3 a, 3 c of the polycrystalline silicon layer3 where the lower electrodes 12 are arranged at a wide pitch have alower film quality than that in the region 3 a where the lowerelectrodes 12 are arranged at a narrow pitch. In FIG. 16, the respectivearrows extending from the heater 40 in the thickness direction of theinsulative substrate 11 schematically indicate the flows of heat to beabsorbed by the lower electrodes 12. The wider horizontal width of thearrow means a larger heat amount to be absorbed.

From this point of view, in the above embodiment, the buffer layer 14 isformed of amorphous silicon which is one of materials capable ofabsorbing infrared rays. Thus, as shown in FIG. 15, in the process offorming the buffer layer 14 to cover the whole area on the side of thefront surface of the insulative substrate 11, and then forming thereonthe non-doped polycrystalline silicon layer 3 to be formed as the driftlayers 6, when the insulative substrate 11 is heated from the side ofthe surface (back surface) opposite to the front surface thereof byusing the heater 40, the temperature distribution on the side of thefront surface of the insulative substrate 11 can be uniformedirrespective of the pattern of the lower electrodes 12 to achieveenhanced in-plane uniformity in film quality of the polycrystallinesilicon layer 3. Thus, as comparted to an electron source in which thebuffer layer 14 is formed only in the region where it is superimposed onthe lower electrode 12, the in-plane variation in quality of the driftlayer 6 can be minimized to reduce the in-plane variation in electronemission characteristic.

In the electron source in the above embodiment, the buffer layer 14 iscomposed of an amorphous layer or amorphous silicon layer. Thus, thebuffer layer 14 can be readily formed through a commonly usedsemiconductor production process (e.g. plasma CVD process) at arelatively low temperature.

While the drift layer 6 in the above embodiment is formed by subjectingthe non-doped polycrystalline silicon layer 3 to a nanocrystallizationprocess, and then subjecting the obtained nanocrystallized layer to anoxidation process, another polycrystalline semiconductor layer may beused as a substitute for the polycrystalline silicon layer 3. Further,while the insulating film in the above embodiment is composed of thesilicon oxide film 64, and formed through an oxidation process, anitriding process or an oxynitriding process may be used as a substitutefor the oxidation process. If the nitriding process is used, each of thesilicon oxide films 52, 64 will be formed as a silicon nitride film. Ifthe oxynitriding process is used, each of the silicon oxide films 52, 64will be formed as a silicon oxynitride film.

While the present invention has been described in conjunction withspecific embodiments, various modifications and alterations will becomeapparent to those skilled in the art. Therefore, it is intended that thepresent invention is not limited to the illustrative embodiments herein,but only by the appended claims and their equivalents.

INDUSTRIAL APPLICABILITY

As mentioned above, the electron source according to the presentinvention is effective to reduce the in-plain variation in electronemission characteristic and provide enhanced reliability thereof. Thus,the electron source is suitable to use in flat light sources, flatdisplay devices or solid-vacuum devices.

1. A field emission electron source comprising an insulative substrateand an electron source element formed on the side of one surface of saidinsulative substrate, said electron source element comprising: a lowerelectrode; a surface electrode; and a strong-field drift layer includingpolycrystalline silicon and disposed between said lower electrode andsaid surface electrode, said strong-field drift layer allowing electronsto pass therethrough according to an electric field generated when acertain voltage is applied to said lower and surface electrodes in sucha manner that said surface electrode has a higher potential than that ofsaid lower electrode, said field emission electron source comprising: abuffer layer provided between said strong-field drift layer and saidlower electrode, said buffer layer having an electrical resistancegreater than that of said polycrystalline silicon, and said buffer layerbeing composed of a film which is uniformly formed over the whole areaon the side of said surface of said insulative substrate.
 2. The fieldemission electron source according to claim 1, wherein said buffer layerincludes an amorphous layer.
 3. The field emission electron sourceaccording to claim 1, in which a plural number of said electron sourceelements are formed on the side of said surface of said insulativesubstrate, wherein said insulative substrate includes a glass substrateallowing infrared rays to transmit therethrough, and said buffer layerincludes a portion of a film which is made of a material capable ofabsorbing infrared rays and formed to cover the whole area on the sideof said surface of said insulative substrate before the formation ofsaid strong-field drift layer.
 4. The field emission electron sourceaccording to claim 3, wherein said amorphous layer includes an amorphoussilicon layer.
 5. The field emission electron source according to claim3, wherein said strong-field drift layer includes anodized porouspolycrystalline silicon.
 6. The field emission electron source accordingto claim 5, wherein said strong-field drift layer includes a pluralityof columnar semiconductor crystals each formed along the thicknessdirection of said lower electrode, and a number of nanometer-ordersemiconductor nanocrystals residing between said semiconductor crystals,each of said semiconductor nanocrystals having a surface formed with aninsulating film which has a thickness less than the grain size of saidsemiconductor nanocrystal.
 7. A method of producing the field emissionelectron source of claim 1, comprising: forming the lower electrode onthe side of said surface of said insulative substrate, and then formingthe buffer layer on said lower electrode before forming the strong-fielddrift layer.
 8. A method of producing the field emission electron sourceof claim 6, comprising: forming the lower electrode on the side of saidsurface of said insulative substrate; forming step of forming the bufferlayer on the side of said surface of said insulative substrate aftersaid lower-electrode forming step; forming a polycrystallinesemiconductor layer on the surface of said buffer layer;nanocrystallizing at least a portion of said polycrystallinesemiconductor layer through an anodizing process to form thesemiconductor nanocrystals; and forming the insulating film on thesurface of each of said semiconductor nanocrystals.
 9. The methodaccording to claim 8, wherein the forming of the polycrystallinesemiconductor layer is performed after the forming of the buffer layerwithout exposing the surface of said buffer layer to the atmosphere. 10.The method according to claim 9, in which a plasma CVD process is usedas a film-forming process in forming the buffer layer andpolycrystalline semiconductor layer wherein when the forming of thebuffer layer is shifted to the forming the polycrystalline semiconductorlayer, a discharge power for said plasma CVD process is changed from afirst condition for forming the buffer layer to a second condition forforming the polycrystalline semiconductor layer.
 11. The methodaccording to claim 9, in which a plasma CVD process is used as afilm-forming process in forming the buffer layer and polycrystallinesemiconductor layer, wherein when the forming of the buffer layer isshifted to the forming the polycrystalline semiconductor layer, adischarge pressure for said plasma CVD process is changed from a firstcondition for forming the buffer layer to a second condition for formingthe polycrystalline semiconductor layer.
 12. The method according toclaim 9, in which a plasma CVD process or catalytic CVD process is usedas a film-forming process in forming the buffer layer andpolycrystalline semiconductor layer, wherein when the forming of thebuffer layer is shifted to the forming the polycrystalline semiconductorlayer the partial pressure ratio of source gases for said plasma CVDprocess or catalytic CVD process is changed from a first condition forforming the buffer layer to a second condition for forming thepolycrystalline semiconductor layer.
 13. The method according to claim9, in which a plasma CVD process or catalytic CVD process is used as afilm-forming process in forming the buffer layer and polycrystallinesemiconductor layer, wherein when the forming of the buffer layer isshifted to the forming the polycrystalline semiconductor layer, the kindof source gases for said plasma CVD process or catalytic CVD process ischanged from a first condition for forming the buffer layer to a secondcondition for forming the polycrystalline semiconductor layer.
 14. Themethod according to claim 8, which includes between forming the bufferlayer and polycrystalline semiconductor layer, a pre-growth treatment ofsubjecting the surface of the buffer layer to a treatment forfacilitating the creation of a crystal nucleus in the initial stage offorming the polycrystalline semiconductor layer.
 15. The methodaccording to claim 14, wherein said pre-growth treatment comprisessubjecting the surface of said buffer layer to a plasma treatment. 16.The method according to claim 14, in which said pre-growth treatmentcomprises subjecting the surface of said buffer layer to a hydrogenplasma treatment, wherein forming the polycrystalline semiconductorlayer includes forming a polycrystalline silicon layer serving as thepolycrystalline semiconductor layer through a plasma CVD process using asource gas including at least a silane-based gas.
 17. The methodaccording to claim 14, wherein said pre-growth treatment comprisessubjecting the surface of said buffer layer to an argon plasmatreatment.
 18. The method according to claim 14, wherein said pre-growthtreatment comprises forming a layer including a number of siliconnanocrystals, on the surface of said buffer layer.